This invention relates to data processing systems; and more particularly, it relates to architectures for such systems which are "expandable by a factor of two", "partitionable", and "place a low overhead on the entry level system".
As used herein, a data processing system architecture is expandable by a factor of two if it includes a small or "entry level system" to which modules can be added to thereby form an "upgraded system" which has twice the processing capacity of the entry level system. Also as used herein, the upgraded system is "partitionable" when one portion of that system can be powered down for repairs while the remaining portion can continue to operate at a reduced capacity.
Now in addition to being expandable by a factor of two and being partitionable, it is highly desirable that those features be provided without greatly increasing the cost or overhead to the entry level system. Otherwise, the entry level system will be too expensive to compete with other entry level systems which third parties may offer with similar computing capacity but without the expandable and partitionable features. On the other hand, a significant marketing advantage would be obtained if an entry level system could be provided which is expandable by a factor of two to a partitionable upgraded system at essentially the same cost as an entry level system which does not have those features.
In the prior art, one entry level data processing system which is expandable by a factor of two is disclosed in U.S. patent application 08/019,003 by Tran et al and assigned to the present assignee. However, each module of the entry level system of that patent (e.g. the central processing module and memory modules) must have two system bus ports--only one of which is used in the entry level system, and the other of which is required solely for expandability. Thus, the overhead to the entry level system is 1) the second system bus, 2) the second system bus port on each module, 3) a two-to-one multiplexor which must be provided in each module to selectively transmit and receive data from the two system bus ports, and 4) control circuits which must provided in each module for the multiplexor.
Further, the above upgraded data processing system of Tran et al is not partitionable as defined above. This is because in the upgraded system, the system busses run directly to all of the modules in the system (e.g.--the two central processing modules). Thus there is no way to open circuit the system busses and power down one central processing module while the other processing module runs.
Accordingly, a primary object of the invention is to provide an entry level data processing system which is expandable by a factor of two to a partitionable upgraded system with very little overhead to the entry level system.